Final Program

ARTS23 Preliminary Program

Thursday 12th of October

4:00 PM – 4:10 PM (PDT time)

Opening session

4:10 PM – 5:00 PM (PDT time)

Keynote: Chen He, Ph.D. Fellow and Senior Director of Product Enablement, Automotive Processing

Challenges and Solutions for Automotive Semiconductor Quality, Reliability, and Functional Safety

NXP Semiconductors, US

Chen He is a Fellow and Senior Director at NXP Semiconductors. With a PhD degree in Computer Engineering from the University of Texas at Austin, he has more than 24 years of experience and leadership in automotive microcontrollers and processors development, especially the area of Zero Defect (ZD) stress and test methodology. He is the “father” of the Advanced Burn-In methodology which has saved tens of millions of dollars each year and improved quality at the same time for automotive products at NXP. His interests also include embedded Non-Volatile Memory (NVM) and Machine Learning (ML) applications to test. Chen has been issued 32 US patents and published over 40 technical papers. He has served as panelist and program committee member and given invited talks at multiple IEEE conferences. He has been elected to IEEE Fellow for his contributions to test of automotive microcontrollers and microprocessors since 2023.

5:00 PM – 6:30 PM (PDT time)

Technical Session 1 – Automotive Chip Reliability and Resilience
Moderator: Davide Appello – Technoprobe (IT)

Meirav Nitzan, Nir Maor, Rahul Gulati, Antonio Priore and Alexander Giessing.
Using High Resilience Flip Flops to Improve Transient Faults Risk Reduction for Automotive
Qualcomm (US), Qualcomm (UK), Exida (DE)

Kranthi Kandula , Ramalingam Kolisetti, Yervant Zorian, Gurgen Harutyunyan, Grigor Tshagharyan
SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor
Synopsys (IND)

Anil Ranjitbhai Patel and Peter Liggesmeyer.
LADRI: LeArning-based Dynamic Risk Indicator in Automated Driving System
RPTU Kaiserslautern-Landau (DE)

Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O’Connor, Bastien Deveautour, Ernesto Sanchez and Alberto Bosio.
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator
Ecole Central de Lyon – INL (FR), Politecnico di Torino (IT)

6:30 PM – 7:30 PM (PDT time)

Welcome Reception

Friday 13th of October

8:30 AM – 9:20 AM (PDT time)

Technical 2 : Automotive Testing Techniques
Moderator: Ric Dokken – Roguevation (US)

Noam Brousard, Andrea Matteucci, Alam Akbar and Gal Carmel.
Prognostics and Monitoring of Automotive Electronics Using On-Chip Telemetry
Proteantecs (US)

Alessandro Maseri, Luca Moriconi and Giovanni Taormina.
RETE: Design and Test for Reliability – Data Analysis for Zero Defects
ELES (IT) – STMicroelectronics (IT)

9:20 AM – 10:00 AM (PDT time)
Moderator: Ralf Montino – Elmos (DE)

Anthony Coyette.
Embedded tutorial – Analog Testing in Automotive

10:00 AM – 10:30 AM (PDT time)

Coffee Break

10:30 AM – 12:00 PM (PDT time)

Technical Session 3 – Analog Testing Solutions for Automotive Chips
Moderator: Anne Meixner – The Engineers’ Daughter LLC (US)

Stefano Roggi, Josef Niederl and Jaafar Mejri.
Built-In Self-Test for Charge Redistribution SARADCs
Infineon Technologies (AU)

Mona Ganji and Degang Chen.
Built-In Self-Test Defect Detection and Localization for SAR ADC
Iowa State University (US)

Leela Krishna Thota, Varun Reddy and Sreenivasa Rao Vuttaravilli.
Analog/Mixed-signal Fault Analysis using Custom Fault Approach
Synopsys (IND)

12:00 PM – 1:00 PM (PDT time)


1:00 PM – 2:30 PM (PDT time)

Panel on Functional Safety

Moderator : Nir Maor, Qualcomm (US)

Jyotika Athavale, Synopsys (US)
Chen He, NXP (US)
Meirav Nitzan, Qualcomm (US)
Prashant Kulkarni, ARM (UK)

2:30 PM – 2:40 PM (PDT time)

Short “human factor” Break

2:40 PM – 3:55 PM (PDT time)

Special Session – Machine Learning Techniques for Functional Safety evaluation
Organizer and Moderator: Prasanth Viswanathan Pillai, Texas Instruments (IND)

Slimane Boutobza
Improving Functional Safety Through ML Enabled Test Point Insertion Techniques
Cadence (FR)

Nirmal Saxena, Yanxiang Huang
On Quantifying Functional Safety Metrics using AI—A Perspective

Arjun Chaudhuri, Krishnendu Chakrabarty
Safety Criticality Analysis and Test Generation for Structural Faults Using Neural Twins
NVIDIA, Arizona State University (US)

3:55 PM – 4:00 PM (PDT time)

Closing session