Thursday 29th of September 4:00 PM – 4:10 PM (PDT time)
Opening session
General Chair
Yervant Zorian, Synopsys – US
Program Chair
Paolo Bernardi, Politecnico di Torino – IT
Thursday 29th of September 4:10 PM – 5:10 PM (PDT time)
Keynoter 1
Journey from Mobile to Automobile: Leverage Learn Lead
Sundarrajan Subramanian, Vice President, Qualcomm
Bio: Sundarrajan Subramanian is VP Engineering at Qualcomm Bangalore and is responsible for managing the SoC Front-End organization for India HW. The SoC Front-End functions include Design, Design Verification (DV), Design-For-Test (DFT) and Security, Power management, Debug cores development. The SoC Front-End teams in India ( Bangalore, Noida and Hyderabad) are responsible to deliver end to end products spanning multiple technology nodes and varied markets across Mobile, IoT, Automotive, XR etc. Sundar’s previous responsibilities at Qualcomm include leading the SoC development and productization for Qualcomm thin modems across multiple generations. He has held positions previously at Teradyne (USA), Cisco Systems ( USA), Texas Instruments ( India) in the areas of Design-For-Test (DFT), Implementation, Post Si debug, Design Management . Sundar has been in the VLSI industry for more than 24 years and has a Master’s degree in Solid State Electronics from Arizona State University , USA.
Abstract: The Automobile as we know it, is going through a revolutionary structural transformation from the traditionally known mechanical assembly to now an electronics-dominated transportation entity. This new avatar of the automobile is providing a compelling and enriching user experience that is transforming the way we drive. This talk will touch upon the challenges and opportunities that exist for the semiconductor industry in driving this change. It will provide an overview of Qualcomm’s experience in leveraging its mobile expertise built over 3 decades and scaling it to the Automobile market – spanning telematics, in-Vehicle Infotainment and autonomous driving segments. The journey from mobile to automobile will draw parallels and contrasts showcasing various aspects of semiconductor Design, Verification & Test.
Thursday 29th of September 5:10 PM – 6:30 PM (PDT time)
Technical Session 1 – Functional Safety Solutions
Moderator: Michele Portolan – Grenoble U., FR
Realization of low power POST with a hybrid test pattern reduction technique
Yoichi Maeda, Yoshinori Nishida, Hiroyuki Iwata, Jun Matsushima, Tatsuya Saito – Renesas, JP
DFT and Functional Safety Challenges for Mixed Signal MCUs in Automotive Applications
Malav Shah – Texas Instruments, IND
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip
Giusy Iaria, Gabriele Filipponi, Matteo Sonza Reorda – Politecnico di Torino, IT
Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre – STMicroelectronics, IT
Thursday 29th of September 7:00 PM – 9:00 PM (PDT time)
Reception – Adventure Lawn garden
Friday 30th of September 8:30 AM – 9:20 AM (PDT time)
Keynoter 2
Evolution and Trends driving the Automotive Architecture and Ecosystems of the future
Vasanth Waran, Senior Director, Synopsys
Bio: Vasanth Nanjundes Waran is a Senior Director of Automotive Business Development and Strategy at Synopsys. He assists Automotive OEMs and partners in designing the next generation of Automotive Compute, Zone controllers and architectural solutions for the Software defined car of the future. Prior to his role with Synopsys, he defined and managed the industry’s most successful Automotive compute SOC portfolio at Qualcomm Inc and was instrumental in growing the Automotive Business. Prior to this, he had various roles at Intel in Engineering, Quality & Reliability and Platform marketing for Automotive solutions.
Abstract: New use-cases and architectures are driving changes in the manner in which automotive Electronic Control Units (ECUs) are being designed. OEMs and their suppliers are gearing towards a changing landscape precipitated by adoption of Autonomous vehicles, new designs for EVs and business model transformation (Maas for e.g). How do auto-makers and their ecosystem partners adapt to these new paradigms and address advanced compute and s/w solutions in this new landscape? We’ll discuss the changes that the Automotive supply chain, including SOC suppliers, tier-1s and tier-2, HW & SW partners are embracing to address these new challenges.
Friday 30th of September 9:20 AM – 10:10 AM (PDT time)
Technical Session 2 – Memory test and reliability
Moderator: Malav Shah – TI, IND
High-Coverage DfT and Reliability Enhancements for Automotive Floating Gate OTP Beyond AEC-Q100
Hans Martin von Staudt, Franz Schuler – Dialog Semiconductor – A Renesas Company, DE
Rohitaswa Bhattacharya – Dialog Semiconductor – A Renesas Company, UK
Justin Wei-Lin Cheng, Cheng-Da Huang, Parker Chih-Chun Chen – eMemory Technology Inc, TW
A Novel Protection Technique for Embedded Memories with Optimized PPA
Costas Argyrides, Vilas Sridharan – AMD, US
Hayk Danoyan, Gurgen Harutyunyan – Synopsys, AR
Coffee Break
Friday 30th of September 10:40 AM – 12:00 PM (PDT time)
Technical Session 3 – In-field testing
Moderator: Giorgio Insinga – Politecnico di Torino, IT
In-System-BIST Challenges
Nir Maor – Qualcomm, US
Functional Safety Challenges and Solutions for the arm® MaliTM-G78AE GPU IP
Prashant Kulkarni, Kartik Kathuria – ARM, UK (remote presentation)
Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics
Andrea Matteucci, Nir Sever – proteanTecs, ISR (remote presentation)
Alex Burlak, Marc Hutner – proteanTecs, US
Lunch
Friday 30th of September 1:00 PM – 2:15 PM (PDT time)
Special Session – The Accellera Functional Safety Standard: enabling automation, interoperability and traceability
Organizer: Alessandra Nardi, Accellera FS WG Chair
Bio: Alessandra Nardi, PhD, is a Distinguished Architect leading the Advanced Platforms Solutions team at Synopsys. She is responsible for a cross-functional team driving development and adoption of EDA solutions for functional safety, security and reliability. After her postdoc at the University of California, Berkeley, she held various R&D lead positions at Magma Design Automation, Synopsys and Cadence spanning statistical static timing analysis, library characterization, power integrity and functional safety. Alessandra holds a MS and a PhD in Electrical Engineering from the University of Padova, Italy.
Special session abstract: For safety critical applications, standards (e.g. ISO26262) are readily available to define processes and norms to comply with Functional Safety requirements. Implementing these processes during the lifecycle poses challenges during the exchange and integration of functional safety data between different work products and activities among different teams and different layers of the supply chain. Also, automation tools are now available to support design and verification flows that are functional safety aware, however interoperability among them is not fully available yet. The Accellera Functional Safety Working Group is defining a language to capture the functional safety data, which is the set of data needed to perform safety activities and to generate work products. This session will provide an update of the activities of the Working Group, sharing details about the underlying data model, the formalization process that led to it and examples of utilization and underlying methodologies. It will also briefly preview some future activities to expand the initial data model that has so far focused on FMEDA (Failure Mode Effects and Diagnostic Analysis).
Speakers:
Bala Chavali, Principal Member of Technical Staff – AMD, US
Alessandra Nardi – Distinguished Architect, Synopsys, US
Ghani Kanawati – Technical Director of Functional Safety, ARM, UK
Short “human factor” Break
Friday 30th of September 2:30 PM – 3:45 PM (PDT time)
Technical Session 4 – Simulation and fault simulation techniques
Moderator: Grigor Tshagharyan – Synopsys, AR
A guided debugger-based fault injector for flow evaluation of functional test programs
Francesco Angione, Nicola di Gruttola Giardino, Davide Piumatti, Matteo Sonza Reorda – Politecnico di Torino, IT
Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre – STMicroelectronics, IT
Estimating Performance and Power Dissipation of ADAS Application on RTL
Magdy El-Moursy – Siemens EDA, US
Friday 30th of September 3:45 PM – 4:00 PM (PDT time)
Closing session