All times are CET
Thursday, May 28th, 2026
| 16:30 – 16:45 | Opening Session |
| 16:45 – 17:30 | Keynote 1: Challenges for verification validation and test of components and systems in the era of rapid increase of complexity and overall presence of AI systems |
| 17:30 – 18:30 | Panel on AI for Automotive |
| 18:30 – 19:10 | Technical Session 1 |
| 19:30 | Dinner |
Friday, May 29th, 2026
| 08:30 – 09:15 | Keynote 2: The Advent of Analog Scan |
| 09:15 – 10:15 | Panel on Analog Scan |
| 10:15 – 11:00 | Embedded Tutorial: FuSa meets LLM: From Functional Safety Requirements to Traceable Fault Criticality |
| 11:00 – 11:30 | Coffee break |
| 11:30 – 12:30 | Technical Session 2 |
| 12:30 – 14:30 | Lunch Break |
| 14:30 – 15:30 | Technical Session 3 |
| 15:30 | Closing |
Thursday, May 28th, 2026
16:30 – 16:45 Opening
Yervant Zorian (Synopsys, US)
Davide Appello (Technoprobe, IT)
Wim Dobbelaere (onsemi, BE)
Giusy Iaria (Politecnico di Torino, IT)
16:45 – 17:30 Keynote 1
Title: Challenges for verification validation and test of components and systems in the era of rapid increase of complexity and overall presence of AI systems
Anton Chichkov (Chips Joint Undertaking, BE)
Abstract:
With the expected continuous progress in automated driving, driven by the introduction of advanced sensor technologies, high-performance computing, machine learning, computer vision, data fusion techniques, AI, and other system technologies, testing is facing ever-increasing challenges.
Consequently, there is a strong need to develop new testing methods in order to guarantee quality. These methods may include, but are not limited to, accelerated testing, residual risk quantification, virtual testing and simulation, as well as a deeper link between component testing and system-level scenario and behaviour testing.
Anton Chichkov is Head of Programmes and Communication at Chips JU, with 37 years of experience across the electronic components and systems (ECS) landscape. Holding a PhD in Computer Science from the Technical University of Lisbon and a background in chip design and test, he has worked across industry and research from semiconductor equipment manufacturing and RTO researcher to a decade in semiconductor manufacturing. He later joined ENIAC JU and now contributes to shaping Europe’s semiconductor ecosystem through Chips JU.
17:30 – 18:30 Panel on AI for Automotive
Moderator: Riccardo Cantoro (Politecnico di Torino)
Abstract: This panel discusses the growing role of artificial intelligence in automotive electronics, focusing on its impact across the engineering flow, in-vehicle applications, and AI-oriented hardware platforms. Panelists will examine how AI is reshaping design, verification, test, diagnosis, reliability, and functional safety, while also addressing the challenges posed by AI accelerators and AI-centric SoCs. The discussion will explore current limitations, standardization gaps, and open research challenges, with the goal of identifying realistic, trustworthy, and safe paths for deploying AI in future automotive systems.
Panelists:
- Marcello Traiola (INRIA, France)
- Paolo Bernardi (Politecnico di Torino, Italy)
- Marco Restifo (ARM, United Kingdom)
- Giorgia Cassetta (Infineon, Germany)
18:30 – 19:10 Technical Session 1
Moderator: TBA
- LLM-Driven Autonomous SBST Generation for RISC-V Processors
Changhao Wang, Nicolò Bellarmino, Riccardo Cantoro, Giovanni Squillero, Yijing Chen and Josie Esteban Rodriguez Condia (Politecnico di Torino, Italy)
2. Use of GitHub Copilot Agent Mode for Automated Development in R&D Data Engineering
Marco D’Acunzo (Infineon Techologies, Italy), Giorgia Cassetta (Infineon Techologies, Germany), Daniele Rossi and Maamoun Jamal Mohamad (Infineon Techologies, Italy)
19:30 Dinner
Friday, May 29th, 2026
8:30 – 9:15 Keynote 2
The Advent of Analog Scan
Stephen Sunter (Siemens EDA, CA)
Abstract: Digital scan was first reported 60 years ago and widely used 30 years ago. There has never been an equivalent, general DfT and test solution for analog and mixed-signal circuits until now. Ideas from different research groups led to the analog scan solution described in an award-winning paper two years ago. I will briefly review the elements of analog scan, why it can change analog test so much, and some results so far. Superficially, it is remarkably similar to digital scan, but technically it is the first truly structural circuit test method. It is well suited to automotive applications due to its high defect coverage, sub-millisecond test times, and digital-only stimulus and response. But interesting challenges remain, such as the intrusive nature of scan, the high level of redundancy in analog circuits, and the many non-scannable logic gates in their midst.
Stephen Sunter has been working in mixed-signal IC design, test, and design-for-test (DfT) for almost 50 years. He is lead author of over 50 papers (5 of which won ITC Best Paper or Honorable Mention awards) and two dozen US patents on these topics, and co-author/inventor of many others. He has been an Editor of JETTA for over 10 years, an ITC Program Committee member for over 15 years, and a VTS Program Committee member for over 30 years. He is Chair of the IEEE P1687.2 Working Group and a Life Senior Member of IEEE, and he was a Chair of the P2427 Working Group, thrice a Program Chair of the Mixed-Signal Test Workshop (IMSTW), and a Vice-Chair of the P1149.4 WG. At Siemens EDA, formerly Mentor Graphics, he is the Engineering Director for Mixed-Signal DfT, a position he has held for 30 years.
9:15 – 10:15 Panel on Analog Scan
Moderator: Wim Dobbelaere (onsemi, BE)
How could analog scan change the future of automotive?
Abstract: Analog scan has the potential to fundamentally reshape automotive test by enabling a paradigm shift from traditional specification-based testing to a structural digital-based defect-oriented methodology. This panel brings together leading experts to explore its transformative impact on quality, cost, development lead time, manufacturing infrastructure, and engineering roles, while addressing the key challenges and research directions that will determine its adoption in future automotive systems.
Panelists:
- Stephen Sunter (Siemens EDA)
- Anthony Coyette (onsemi, BE)
- Cahyo Primawidodo (Infineon, DE)
- Davide Appello (Technoprobe, IT)
10:15 – 11:00 Embedded Tutorial
Moderator: Giusy Iaria (Politecnico di Torino, IT)
Speaker: Krishnendu Chakrabarty (Arizona State University, US)
Title: FuSa meets LLM: From Functional Safety Requirements to Traceable Fault Criticality
11:00 – 11:30 Coffee Break
11:30 – 12:30 Technical Session 2
Moderator: TBA
- Increasing Test Quality by performing Cell-Aware Defect Characterization for different PVT Corners
Vladimir Zivkovic (Siemens EDA, Denmark), Florian Klemme, Stephan Eggersgluess, Andreas Glowatz and Daniel Tille (Siemens EDA, Germany)
2. Defect‑Oriented Analog Testability Using Ratio‑Based IDDA Measurements with Reconfigurable BIST
Pavel Horsky (onsemi, Czechia)
3. Enhancing Automotive Security using Intel® Partner Security Engine (IPSE)
Pradnya Mane, Srinivas Musti, Tian Teck and Ritu Sethi (Intel, India)
12:30 – 14:30 Lunch break
14:30 – 15:30 Technical Session 3
Moderator: TBA
- Optimizing Scan Test Costs in Automotive SoCs
Giusy Iaria, Paolo Bernardi, Lorenzo Cardone (Politecnico di Torino, Italy), Claudia Bertani, Giuseppe Garozzo and Vincenzo Tancorre (STMicroelectronics, Italy)
2. Gap Analysis between Automotive and Space Standards
Leonidas Kosmidis, Ivan Rodiguez-Ferrandez, Matina Maria Trompouki (Barcelona Supercomputing Center, Spain) and David Steenari (ESA, Netherlands)
3. Testability, safety and cybersecurity concepts applied in case of high volume ultrasonic sensors driving IC’s
Marek Hustava (onsemi, Czechia)
15:30 Closing
Yervant Zorian (Synopsys, US)
Davide Appello (Technoprobe, IT)
Wim Dobbelaere (onsemi, BE)
Giusy Iaria (Politecnico di Torino, IT)