Keynote
More Compute Performance under the Hood: New Applications and Complexity Challenges for Automotive Microcontrollers
Dr. Christian Pacha
Abstract Modern automotive microcontroller are evolving towards heterogeneous SoCs with an increasing HW-SW complexity. The traditional engineering paradigms of high quality and safety requirements are combined with enhanced computational functionalities, high bandwidth communication interfaces, advanced signal processing capabilities and multi-level memory hierarchies. Market driver behind this evolution is the transformation process in the automotive industry, notably hybrid and full electric vehicles, advanced driver assistance systems and autonomous driving as well as new electrical/electronic car architectures.
This talk gives an overview how the diversifying application landscapes motivate new SoC integration paradigms. We will illustrate their impact on SoC architecture and design based on example of Infineon’s Aurix family. Typical dependencies across the development value chain ranging from the initial conceptual phase to post-Silicon, such as power-performance and thermal integrity, will be presented and analyzed considering generic industry trends in scaled microelectronics.
About the speaker
Christian Pacha received the Dipl.-Phys. and Dr.-Ing. degrees from the University of Dortmund, Germany, in 1996 and 2001, respectively. From 1996 to 2000, he was with the Department of Microelectronics, University of Dortmund. In 2000, he joined Infineon Technologies, Corporate Research, Munich, Germany and moved to the Advanced Systems and Circuits development team in 2005. In 2011, he joined the Intel Wireless Communication Group as principal engineer and focussed on low power concepts in 28nm and 14nm CMOS generations for multiple LTE and 5G mobile SoCs and platforms. He returned to Infineon Technologies in 2018 as Senior Principal, where he currently leads the SoC Architecture team in the Automotive Microcontroller development. With his team, he is working in the areas power-performance optimization, technology-design interdependencies, SoC-SiP partitioning, memories, and SoC interconnects for future microcontrollers. He has authored or co-authored more than 40 technical publications and holds about 25 patents.
Embedded tutorial
Memory Testing for Automotive Applications beyond plain Test Quality
Dr. Martin Keim
Abstract Everyone understands that automotive applications demand the highest test quality. This is true for logic testing as well as for memory testing. But the story does not end with just high quality tests. In fact, quality is just one of many critical aspects implementing memory testing for such applications. In this short embedded tutorial, we will touch on several such aspects, including Memory BIST IP design and qualification, EDA tool requirements, algorithm selection and qualification, test application and repair, design and system interaction, all the way to diagnosis of field returns.
About the speaker
Dr. Martin Keim joined the Design-for-Test group of Mentor Graphics in 2001, now Tessent Silicon Lifecycle Solutions in Siemens EDA, where he is Engineering Director responsible for Memory Built-In Self-Test, Silicon Insight, and the IJTAG Infrastructure teams. He is secretary of the IEEE P1687.1 working group and was member of the IEEE 1687 working group. He was editor of the sixth edition of the Microelectronics Failure Analysis Desk Reference Manual, responsible for the test and diagnosis chapters. Dr. Keim is active in the test and failure analysis community, member of several program committees, and was General Chair of International Symposium for Testing and Failure Analysis in 2016. He holds numerous international patents and is author of many technical publications. He received a doctorate in Informatics from the Albert-Ludwigs University in Germany.